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september 2004 dsc-2967/12 1 ?2004 integrated device technology, inc. features high-speed address/chip select access time ? military: 20/25/35/45/55/70/85/100ns (max.) ? industrial: 25/35ns (max.) ? commercial: 15/20/25/35ns (max.) low power consumption battery backup operation ? 2v data retention voltage (l version only) produced with advanced cmos high-performance technology inputs and outputs directly ttl-compatible three-state outputs available in 28-pin dip, cerdip and soj military product compliant to mil-std-883, class b description the idt7164 is a 65,536 bit high-speed static ram organized as 8k x 8. it is fabricated using idt?s high-performance, high-reliability cmos technology. address access times as fast as 15ns are available and the circuit offers a reduced power standby mode. when cs 1 goes high or cs 2 goes low, the circuit will automatically go to, and remain in, a low- power stand by mode. the low-power (l) version also offers a battery backup data retention capability at power supply levels as low as 2v. all inputs and outputs of the idt7164 are ttl-compatible and operation is from a single 5v supply, simplifying system designs. fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. the idt7164 is packaged in a 28-pin 300 mil dip and soj and a 28- pin 600 mil cerdip. military grade product is manufactured in compliance with the latest revision of mil-std-883, class b, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. functional block diagram address decoder 65,536 bit memory array i/o control 2967 drw 01 we cs v cc gnd i/o 0 i/o 7 control logic oe 2 cs 1 a 0 a 12 0 7 idt7164s idt7164l cmos static ram 64k (8k x 8-bit)
2 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and industrial temperature ranges pin configurations pin descriptions absolute maximum ratings (1) dip/soj top view truth table (1,2,3) recommended operating temperature and supply voltage recommended dc operating conditions 2967 drw 02 5 6 7 8 9 10 11 12 a 12 1 2 3 4 24 23 22 21 20 19 18 17 d28-1 d28-3 p28-1 p28-2 so28-5 13 14 28 27 26 25 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 v cc we a 8 a 9 a 11 oe a 10 cs 1 i/o 7 16 15 i/o 2 gnd i/o 6 i/o 5 i/o 4 i/o 3 nc cs 2 , name description a 0 - a 12 address i/o 0 - i/o 7 data input/output cs 1 chip select cs 2 chip select we write enable oe output enable gnd ground v cc power 2 967 tbl 01 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v cc + 0.5v. symbol rating com'l. mil. unit v te rm (2 ) terminal voltage with respect to gnd -0.5 to +7.0 -0.5 to +7.0 v t a operating te m p e r a t u r e 0 to +70 -55 to +125 o c t bias te m p e r a t u r e under bias -55 to +125 -65 to +135 o c t stg storage temperature -55 to +125 -65 to +150 o c p t power dissipation 1.0 1.0 w i out dc output current 50 50 ma 2967 tbl 02 notes: 1. cs 2 will power-down cs 1 , but cs 1 will not power-down cs 2 . 2. h = v ih , l = v il , x = don't care. 3. v lc = 0.2v, v hc = v cc - 0.2v we cs 1 cs 2 oe i/o function x h x x high-z deselected - standby (i sb ) x x l x high-z deselected - standby (i sb ) x v hc v hc or v lc x high-z deselected - standby (i sb1 ) xxv lc x high-z deselected - standby (i sb1 ) h l h h high-z output disabled hl h ldata out read data ll hxdata in write data 2967 tbl 03 grade temperature gnd vcc military -55 o c to +125 o c0v 5v 10% industrial -40 o c to +85 o c0v 5v 10% commercial 0 o c to +70 o c0v 5v 10% 2967 tbl 04 note: 1. v il (min.) = ?1.5v for pulse width less than 10ns, once per cycle. symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ v cc + 0.5 v v il input low voltage -0.5 (1 ) ____ 0.8 v 2967 tbl 05
6.42 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and i ndustrial temperature ranges 3 dc electrical characteristics (1) (v cc = 5.0v 10%, v lc = 0.2v, v hc = v cc - 0.2v) capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is determined by device characterization, but is not production tested. symbol parameter (1) conditions max. unit c in input capacitance v in = 0v 8 pf c i/ o i/o capacitance v out = 0v 8 pf 2967 tbl 06 symbol parameter power 7164s15 7164l15 7164s20 7164l20 7164s25 7164l25 unit com'l. com'l. mil. com'l. ind. mil. i cc1 operating power supply current cs 1 = v il , cs 2 = v ih , outputs open v cc = max., f = 0 (2) s 110 100 110 90 90 110 ma l 100 90 100 80 80 100 i cc2 dynamic operating current cs 1 = v il , cs 2 = v ih , outputs open v cc = max., f = f max (2 ) s 180 170 180 170 170 180 ma l 150 150 160 150 150 160 i sb standby power supply current (ttl le ve l), cs 1 > v ih , cs 2 < v il , outputs open, v cc = max., f = f max (2 ) s 20 2020202020 ma l 3 35335 i sb1 full standby power supply current (cmos lev el), f = 0 (2 ) , v cc = max. 1. cs 1 > v hc and cs 2 > v hc , or 2. cs 2 < v lc s 15 1520151520 ma l 0.2 0.2 1 0.2 0.2 1 2967 tbl 0 7 notes: 1. all values are maximum guaranteed values. 2. f max = 1/t rc (all address inputs are cycling at f max ); f = 0 means no address input lines are changing. symbol parameter power 7164s35 7164l35 7164s45 7164l45 7164s55 7164l55 7164s70 7164l70 7164s85/100 7164l85/100 unit com'l. ind . mil. mil. mil. mil. mil. i cc1 operating power supply current cs 1 = v il , cs 2 = v ih , outputs open v cc = max., f = 0 (2) s 90 90 100 100 100 100 100 ma l80809090909090 i cc2 dynamic operating current cs 1 = v il , cs 2 = v ih , outputs open v cc = max., f = f max (2 ) s 150 150 160 160 160 160 160 ma l 130 130 140 130 125 120 120 i sb standby power supply current (ttl level), cs 1 > v ih , cs 2 < v il , outputs open, v cc = max., f = f max (2 ) s20202020202020 ma l3355555 i sb1 full standby power supply current (cmos level), f = 0 (2) , v cc = max. 1. cs 1 > v hc and cs 2 > v hc , or 2. cs 2 < v lc s15152020202020 ma l0.20.211111 2967 tbl 08
4 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and industrial temperature ranges dc electrical characteristics (v cc = 5.0v 10%) ac test conditions *includes scope and jig capacitances figure 2. ac test load (for t clz1, t clz2 , t olz , t chz1, t chz2 , t ohz , t ow , and t whz ) figure 1. ac test load data retention characteristics over all temperature ranges (l version only) (v lc = 0.2v, v hc = v cc - 0.2v) 2967 drw 03 480 ? 30pf* 255 ? data out 5v , 2967 drw 04 480 ? 5pf* 255 ? data out 5v , symbol parameter test conditions idt7164s idt7164l unit min. max. min. max. |i li | input leakage current v cc = max., v in = gnd to v cc mil. com'l. & ind ____ ____ 10 5 ____ ____ 5 2a |i lo | output leakage current v cc = max., cs 1 = v ih , v out = gnd to v cc mil. com'l. & ind ____ ____ 10 5 ____ ____ 5 2a v ol output low voltage i ol = 8ma, v cc = min. ____ 0.4 ____ 0.4 v i ol = 10ma, v cc = min. ____ 0.5 ____ 0.5 v oh output high voltage i oh = -4ma, v cc = min. 2.4 ____ 2.4 ____ v 2967 tbl 09 notes: 1. t a = +25c. 2. t rc = read cycle time. 3. this parameter is guaranteed by device characterization, but is not production tested. typ. (1 ) v cc @ max. v cc @ symbol parameter test condition min. 2.0v 3.0v 2.0v 3.0v unit v dr v cc for data retention ____ 2.0 ____ ____ ____ ____ v i ccdr data retention current mil. com'l. & ind ____ ____ 10 10 15 15 200 60 300 90 a t cdr (3 ) chip deselect to data retention time 1. cs 1 > v hc cs 2 > v hc , or 2. cs 2 < v lc 0 ____ ____ ____ ____ ns t r (3) operation recovery time t rc (2) ____ ____ ____ ____ ns i i li i (3) input leakage current ____ ____ ____ 22 a 2 967 tbl 10 inp ut pulse le ve ls inp ut rise /fall time s inp ut timing re fe re nce le ve ls output reference levels ac test load gnd to 3.0v 5ns 1.5v 1.5v see figures 1 and 2 2967 tbl 11
6.42 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and i ndustrial temperature ranges 5 ac electrical characteristics (v cc = 5.0v 10%, all temperature ranges) notes: 1. 0 to +70c temperature range only. 2. 0 to +70c and ?55c to +125c temperature ranges only. 3. both chip selects must be active for the device to be selected. 4. this parameter is guaranteed by device characterization, but is not production tested. symbol parameter 7164s15 (1 ) 7164l15 (1 ) 7164s20 (2 ) 7164l20 (2 ) 7164s25 7164l25 7164s35 7164l35 unit min. max. min. max. min. max. min. max. read cycle t rc read cycle time 15 ____ 20 ____ 25 ____ 35 ____ ns t aa address access time ____ 15 ____ 19 ____ 25 ____ 35 ns t acs1 (3) chip select-1 access time ____ 15 ____ 20 ____ 25 ____ 35 ns t acs2 (3) chip select-2 access time ____ 20 ____ 25 ____ 30 ____ 40 ns t clz1,2 (4) chip select-1, 2 to output in low-z 5 ____ 5 ____ 5 ____ 5 ____ ns t oe output enable to output valid ____ 7 ____ 8 ____ 12 ____ 18 ns t olz (4) output enab le to output in low-z 0 ____ 0 ____ 0 ____ 0 ____ ns t chz1 ,2 (4 ) chip select-1,2 to output in high-z ____ 8 ____ 9 ____ 13 ____ 15 ns t ohz (4 ) output disab le to output in high-z ____ 7 ____ 8 ____ 10 ____ 15 ns t oh output hold from address change 5 ____ 5 ____ 5 ____ 5 ____ ns t pu (4) chip select to power up time 0 ____ 0 ____ 0 ____ 0 ____ ns t pd (4) chip deselect to power down time ____ 15 ____ 20 ____ 25 ____ 35 ns write cycle t wc write cycle time 15 ____ 20 ____ 25 ____ 35 ____ ns t cw1, 2 chip select to end-of-write 14 ____ 15 ____ 18 ____ 25 ____ ns t aw address valid to end-of-write 14 ____ 15 ____ 18 ____ 25 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 14 ____ 15 ____ 21 ____ 25 ____ ns t wr1 write recovery time ( cs 1 , we )0 ____ 0 ____ 0 ____ 0 ____ ns t wr2 write recovery time (cs 2 )5 ____ 5 ____ 5 ____ 5 ____ ns t whz (4) write enable to output in high-z ____ 6 ____ 8 ____ 10 ____ 14 ns t dw data to write time overlap 8 ____ 10 ____ 13 ____ 15 ____ ns t dh1 data hold from write time ( cs 1 , we )0 ____ 0 ____ 0 ____ 0 ____ ns t dh2 data hold from write time (cs 2 )5 ____ 5 ____ 5 ____ 5 ____ ns t ow (4) output active from end-of-write 4 ____ 4 ____ 4 ____ 4 ____ ns 2967 tbl 12
6 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and industrial temperature ranges ac electrical characteristics (con't.) (v cc = 5.0v 10%, military temperature ranges) notes: 1. both chip selects must be active for the device to be selected. 2. this parameter is guaranteed by device characterization, but is not production tested. symbol parameter 7164s45 7164l45 7164s55 7164l55 7164s70 7164l70 7164s85/100 7164l85/100 unit min. max. min. max. min. max. min. max. read cycle t rc read cycle time 45 ____ 55 ____ 70 ____ 85/100 ____ ns t aa address access time ____ 45 ____ 55 ____ 70 ____ 85/100 ns t acs1 (1) chip select-1 access time ____ 45 ____ 55 ____ 70 ____ 85/100 ns t acs2 (1) chip select-2 access time ____ 45 ____ 55 ____ 70 ____ 85/100 ns t clz1,2 (2) chip select-1, 2 to output in low-z 5 ____ 5 ____ 5 ____ 5 ____ ns t oe output enable to output valid ____ 25 ____ 30 ____ 35 ____ 40 ns t olz (2) output enab le to output in low-z 0 ____ 0 ____ 0 ____ 0 ____ ns t chz1 ,2 (2 ) chip select-1,2 to output in high-z ____ 20 ____ 25 ____ 30 ____ 35 ns t ohz (2 ) output disab le to output in high-z ____ 20 ____ 25 ____ 30 ____ 35 ns t oh output hold from address change 5 ____ 5 ____ 5 ____ 5 ____ ns t pu (2) chip select to power up time 0 ____ 0 ____ 0 ____ 0 ____ ns t pd (2) chip deselect to power down time ____ 45 ____ 55 ____ 70 ____ 85/100 ns write cycle t wc write cycle time 45 ____ 55 ____ 70 ____ 85/100 ____ ns t cw1, 2 chip select to end-of-write 33 ____ 50 ____ 60 ____ 75 ____ ns t aw address valid to end-of-write 33 ____ 50 ____ 60 ____ 75 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 25 ____ 50 ____ 60 ____ 75 ____ ns t wr1 write recovery time ( cs 1 , we )0 ____ 0 ____ 0 ____ 0 ____ ns t wr2 write recovery time (cs 2 )5 ____ 5 ____ 5 ____ 5 ____ ns t whz (2) write enable to output in high-z ____ 18 ____ 25 ____ 30 ____ 35 ns t dw data to write time overlap 20 ____ 25 ____ 30 ____ 35 ____ ns t dh1 data hold from write time ( cs 1 , we )0 ____ 0 ____ 0 ____ 0 ____ ns t dh2 data hold from write time (cs 2 )5 ____ 5 ____ 5 ____ 5 ____ ns t ow (2) output active from end-of-write 4 ____ 4 ____ 4 ____ 4 ____ ns 2967 tbl 13
6.42 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and i ndustrial temperature ranges 7 timing waveform of read cycle no. 1 (1) notes: 1. we is high for read cycle. 2. device is continuously selected, cs 1 is low , cs 2 is high. 3. address valid prior to or coincident with cs 1 transition low and cs 2 transition high. 4. oe is low. 5. transition is measured 200mv from steady state. timing waveform of read cycle no. 2 (1,2,4) timing waveform of read cycle no. 3 (1,3,4) address cs 1 oe data out cs 2 t rc t aa t oh t acs2 t clz2 (5) t oe t acs1 t clz1 (5) t olz (5) t chz2 (5) t ohz (5) t chz1 (5) data valid 2967 drw 05 2967 drw 06 address data out t rc t aa t oh t oh data valid data out t acs2 (5) cs 1 cs 2 t clz2 t acs1 (5) t clz1 t pu t pd i cc i sb t chz2 (5) t chz1 (5) data valid power supply current 2967 drw 07
8 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and industrial temperature ranges timing waveform of write cycle no. 1 ( we controlled timing) (1,5) timing waveform of write cycle no. 2 ( cs controlled timing) (1) notes: 1. a write occurs during the overlap of a low we , a low cs 1 and a high cs 2 . 2. t wr1, 2 is measured from the earlier of cs 1 or we going high or cs 2 going low to the end of the write cycle. 3. during this period, i/o pins are in the output state so that the input signals must not be applied. 4. if the cs 1 low transition or cs 2 high transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. oe is continuously high. if oe is low during a we controlled write cycle, the write pulse width must be the larger of t wp or (t whz +t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse width is as short as the specified t wp . 6. transition is measured 200mv from steady state. address t wc t whz (6) 2967 drw 08 cs 1 data out cs 2 t as t aw t wr1 (2) we t wp t ow (6) data in t dh1,2 t dw data valid (3) (5) address cs 1 cs 2 t wc t as we t cw t wr2 (2) t aw data in t dh1,2 t dw data valid t wr1 (2) (4) 2967 drw 09
6.42 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and i ndustrial temperature ranges 9 ordering information ? commercial low v cc data retention waveform 2967 drw 10 da t a retention mode 4.5v 4.5v v dr 2v v ih v ih t r t cdr v cc cs v dr x power xx speed xxx package x process/ temperature range blank commercial (0c to +70c) y* p** tp* 300 mil soj (so28-5) 600 mil plastic dip (p28-1) 300 mil plastic dip (p28-2) 15 20 25 35 s l standard power low power device type 7164 idt speed in nanoseconds 2967 drw 11 , * available for 15ns and 20ns speed grades only. ** available for 25ns and 35ns speed grades only. x g restricted hazardous substancwe device
10 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and industrial temperature ranges ordering information ? industrial x power xx speed xxx package x process/ temperature range i industrial (?40c to +85c) p y 600 mil plastic dip (p28-1) 300 mil plastic soj (pj28) 25 35 s l standard power low power device type 7164 idt speed in nanoseconds 2967 drw 12 , x g restricted hazardous substance device ordering information ? military x power xx speed xxx package x process/ temperature range b military (?55c to +125c) compliant with mil-std-883, class b d td 600 mil cerdip (d28-1) 300 mil cerdip (d28-3) 20* 25 35 45 55 70 85 100** s l standard power low power device type 7164 idt speed in nanoseconds 2967 drw 13 * available only in 600mil cerdip (d28-1) and 300mil cerdip (d28-1) and 300mil cerdip (d28-3) packaging for a low power. ** available only in 600 mil cerdip (d28-1) packaging.
6.42 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and i ndustrial temperature ranges 11 datasheet document history 1/13/2000 updated to new format pp. 1, 2, 3, 5, 10 added industrial temperature range offerings pp. 1, 3, 9 removed commercial 70ns speed grade offering pp. 1, 3, 6, 10 added 100ns speed grade specification details pg. 3 revised notes and footnotes in dc electrical tables pp. 5, 6 revised notes and footnotes in ac electrical tables pg. 8 removed note 1 from write cycle no. 1 and no. 2 diagrams; renumbered notes and footnotes pp. 9, 10 separated ordering information into commercial, industrial, and military offerings pg. 11 added datasheet document history 08/09/00 not recommended for new designs 02/01/01 removed "not recommended for new designs" 12/07/01 pg. 10 add pj28 to industrial temperature. 09/30/04 pg. 9,10 added "restricted hazardous substance device" to ordering information. corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 sramhelp@idt.com santa clara, ca 95054 fax:408-492-8674 800 544-7726 www.idt.com the idt logo is a registered trademark of integrated device technology, inc.

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